Highest performance IP for graphics, AI/ML The High-Bandwidth Memory generation 2/2E PHY (HBM2E/2 PHY) is silicon-proven and is a…
- Samsung
- 10nm
- LPP
- Available on request
Highest performance IP for graphics, AI/ML The High-Bandwidth Memory generation 2/2E PHY (HBM2E/2 PHY) is silicon-proven and is a…
224G-LR SerDes PHY enables 1.6T and 800G networks
The ever-increasing bandwidth in high-performance computing (HPC) applications is driving the rapid growth of high-speed I/O capa…
High-performance, low-latency PHY for D2D connectivity The UltraLink™ Die-to-Die (D2D) PHY enables SoC providers to deliver more …
The PHY IP for PCI Express® (PCIe®) 5.0 is a high-performance SerDes configurable to operate from 1.25Gbps to 32Gbps in NRZ mode.
10Gbps Multi-Protocol PHY IP (+PCIe 3.1)
10G-KR, XFI, PCIe 3.1/2.0/1.0, XAUI, QSGMII, SGMII, Gigabit Ethernet Growing 10 Gigabit Ethernet deployments in the data centers …
112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
In data center interconnects, short-reach connectivity is needed in use-case scenarios for chip-to-chip, chip-to-optical-module, …
Today’s consumers generate and consume large volumes of data and video, exploding the need for data-intensive processing requirin…
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The l…
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, pr…
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
SerDes requirements for system-on-chip (SoC) designs are becoming increasingly demanding and must support increasing numbers of p…
Audio data transport The Controller IP for MIPI® SoundWire® v1.2 is a fully verified, configurable, digital core that is complian…
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-lo…
Most PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The PHY IP for PCI Express® (PCIe®) …
Highly scalable performance for classic and generative on-device and edge AI solutions
Scalable and Power-Efficient Neural Processing Units The Neo NPUs offer energy-efficient hardware-based AI engines that can be pa…
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Controller IP for CXL addresses…
Universal Chiplet Interconnect Express (UCIe™) Controller
High-bandwidth, low-power and low-latency standardized die-to-die interconnect The Cadence UCIe™ PHY is a high-bandwidth, low-pow…
Ethernet Controller - Configurable MAC solutions for speeds from 10Gbps to 10Mbps
Cadence® Ethernet controller IP family supports the latest Ethernet specifications and provides unmatched flexibility so you can …
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, pr…
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCI Express® (PCIe®) is architected…
Controller IP for the MIPI I3C interface Compliant with the MIPI® I3C® specification and legacy compatible with the I2C specifica…