Vendor: Actt Category: Multi-Protocol PHY

Serdes - SMIC 55nm Eflash

SMIC 55nm LL Silicon Proven View all specifications

Key features

  • 4 TX channels and 4 RX channels;Supports 1.25G~6.25Gbps operation
  • Internal high performance low jitter PLL:RMS jitter < 1.5ps @6.25GHz

Benefits

  • Cost saving compared to eflash technology

What’s Included?

  • Technical documents,GDS hard macro to foundry for IP merge

Silicon Options

Foundry Node Process Maturity
SMIC 55nm LL Silicon Proven

Specifications

Identity

Part Number
XRS55NEFLSERDES_4CHQ6GA
Vendor
Actt

Provider

Actt
HQ: China
Chengdu Analog Circuit Technology Inc. (Actt) Founded in 2011 is a national high-tech enterprise which is specializing in the designing, licensing, the IPs (intellectual property) of the IC (integrated circuit) products, and can provide one-stop service with its clients. Actt has been involved in low power technology field for more than 10 years. As a result, the products structure including ultra-low power analog IP, high reliability and high performance radio frequency IP and high-speed interface IP of Actt has been gradually established. Actt is holding exceeds 200 patents in worldwide, has developed more than 500 IPs, and successively established partnerships with more than 20 fabs on a global scale. It serves hundreds of IC design enterprises worldwide, its products are widely used in 5G, IoT, smart home, automotive electronics, smart power, wearables, medical electronics, industrial control and other fields. Actt always takes it as its responsibility to provide partners with world-leading products and services, adheres to technology innovation as its core value, committing to becoming a trustworthy and innovative world-class IP provider.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is Serdes - SMIC 55nm Eflash?

Serdes - SMIC 55nm Eflash is a Multi-Protocol PHY IP core from Actt listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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