ECO Library IPs at SMIC 40ULP Process
IP
- SMIC
- 40nm
- ULP
ECO Library IPs at SMIC 40ULP Process
IP
ECO Library IPs at SMIC 40LL Process
IP
Foundation IPs at SMIC 40LL Process
IP
USB2.0 Dual-Role PHY, SMIC 55LL
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, SMIC 40LL
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
SMIC 0.13um 1.2V<->3.3V level shifter,1.2v/3.3v operating voltage
SMIC 0.13um 1.2V3.3V Level Shfiter Library
SMIC 0.13um Power Management Kit,1.2v operating voltage
SMIC 0.13um Power Management Kit Library
SMIC 0.13um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.13um 6T HVT High-Density Standard Cell Library
SMIC 0.11um USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The IP is a 3 channel 12-bit DAC based on SMIC 110nm process with maximum current +/- 100mA of one channel.
Mini LVDS Transmitter
IP
IP
SMIC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for SMIC55nm low power 1.2v/2.5v process
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
S55LLRFV25_BLE_02_T is a 2.4GHz ISM band RF Transceiver IP which is designed for Bluetooth Smart applications.
2.5V 12Bit pipeline analog to digital converter
TheS65LLV25_ADC_13 IP is a 2.5V 12Bit pipeline analog to digital converter capable of running at up to 100MHz conversion rate wit…