The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.
- Samsung
- 8nm
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
The GPHY is a fully integrated IP Core with low power consumption for Giga 10/100/1000 Ethernet applications.
SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consum…
PCI Express Gen3 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
USB 2.0 femtoPHY - Samsung 8LPP18 x1, OTG, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 femtoPHY - Samsung 7LPP18 x1, OTG, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 femtoPHY - Samsung 14LPP18 x1, OTG, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 femtoPHY - Samsung 11LPP18 x1, OTG, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 3.0 PHY - Samsung 28LPP18 x1, OTG, North/South (vertical) poly orientation
The USB-C 3.0 and USB 3.0 PHY IP provide designers with the industry's best combination of low area and low power with support fo…
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.
USB-C 3.1/DP TX PHY for Samsung 14LPP, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
USB-C 3.1/DP TX PHY for Samsung 11LPP, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
32G PHY, Samsung 8LPP x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
32G PHY, Samsung 10LPP x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
eUSB2 v1.1 Dual-Role, repeater/native mode PHY, SamSung 28FDSOI, 1.8V, N/S orientation
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 on Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28n…
HDMI 2.0 Receiver with MHL 2.0
IP
MIPI D-PHY v1.2 TX 4 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY v1.2 RX 2 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…