IO pad library IP provides the physical interface between internal core logic and external chip pins. These libraries are critical for signal integrity, ESD robustness, voltage domain interoperability, manufacturability, and reliable chip-level integration across semiconductor products.
Explore IO pad IP libraries including GPIO, analog pads, high-speed pads, and protection structures tailored to foundry process requirements.
TSMC 40LP 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designe…
TSMC 40G Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) p…
TSMC 40G 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designe…
TSMC 40G 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC …
TSMC 40G 2Gb/s RX LVDS IO cell
The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 …
Library of LVDS IOs cells for TSMC 40G
The nSIO2000_TS40G_2V5_0V9 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/0.9V or …
Output Buffer for up to 12Gb/s
The PMCC_OBUF12G is a differential CML 50Ω terminated output driver for datarates from DC up to 12Gb/s.
Programmable Special IO in SMIC0.13um
AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/…
ESD diode and Clamps for 90nm TSMC G/GT/LP
Stand alone ESD diodes and Supply clamping for TSMC 90nm G/GT/LP processes
High Speed Access & Test IP USB Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
High Speed Access & Test IP PCIE Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
The inline CUP I/O library provide 3.3V bi- directional I/O cells with pull -up, pull-down features, Schmitt trigger and a range …
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core po…
The 5V General Purpose I/O libraries provide bidirectional I/O, analog I/O, and a full complement of I/O power, core power, and a…
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, analog I/O, and a full complement of I/O power, core power, and …
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers ope…
The SSTL_15 pad set supports bidirectional single-ended and differential SSTL_15 signaling.
SSTL_15 / SSTL_18 Combo I/O Pad Set
The SSTL_15_18 combo pad set supports bidirectional single-ended and differential SSTL_15 and SSTL_18 signaling.
The subLVDS library provides a subLVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 driver…
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …