Overview
The SSTL_15_18 combo pad set supports bidirectional single-ended
and differential SSTL_15 and SSTL_18 signaling. The driver/receiver pairs, with embedded power cells, are supplied with a full complement of calibration, voltage reference, power, spacer, and adapter cells to assemble a pad ring by abutment. An included rail splitter allows isolated SSTLdomains (1.5V/1.8V) to be placed in the same pad ring with 2.5V/3.3V GPIO domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
Learn more about GPIO IP core
For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.
This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.
One of the critical problems in today’s computing is that transporting data can be more costly in energy and time than computing. With the growing complexity of AI models, SoC designers have shifted their focus toward optimizing memory hierarchies, increasing bandwidth in interconnects, and architecting based on workloads for improved efficiency.
To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.
Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?
