subLVDS I/O Pad Set

The subLVDS library provides a subLVDS driver, receiver, and
temperature stable voltage reference capable of supporting 16 drivers
operating at data rates up to 1600 Mbps. The pad set includes a full
complement of power, spacer, and adapter cells to assemble a
complete pad ring by abutment. An included rail splitter allows
isolated subLVDS domains to be placed in the same pad ring with
other power domains while maintaining continuous VDD/VSS in the
pad ring for robust ESD protection.

• Input receive sensitivity of 50mV peak differential (without hysteresis)
• Common mode range from 0.4V to 1.6V (limited by Power Supply)
• Powered by 1.8V I/O and 1.1V core supplies
• Power consumption: 3.4 mW max @ 800 MHz

• a. Physical abstract in LEF format (.lef)
• b. Timing models in Synopsys Liberty formats (.lib and .db)
• c. Calibre compatible LVS netlist in CDL format (.cdl)
• d. GDSII stream (.gds)
• e. Behavioral Verilog (.v)
• f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
• g. Databook (.pdf)
• h. Library User Guide - ESD Guidelines (.pdf)