VeriSilicon SMIC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library

Overview

Key Features

• SMIC 0.13¦Ìm Logic 1P8M Salicide 1.2V/2.5V process
• Low area and low cost design using DUP technique
• 1.2V core power, 2.5V IO, digital IO supports 3.3V tolerance
• This library includes analog I/O cell part
• Configurable output driving capability with different slew rate
• Supports configurable pull up and pull down resistor
• Supports both CMOS input and Schmitt input with LVTTL compatible
• Provides 2Mhz ~ 27Mhz OSC IO cell
• Suitable for six, seven, or eight metal layers of physical design
• Competitive pad pitch and height

Benefits

• Databook in electronic form
• Verilog models and Synopsys synthesis models
• Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist

Technical Specifications