UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
Overview
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
Technical Specifications
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
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- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler