16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provid…
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Process PG Via ROM Compiler
UMC 28nm HPC Process PG Via ROM Compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm ultra low power via1 ROM complier
UMC 40nm ultra low power via1 ROM complier
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 28HPC process standard synchronous high density TCAM memory compiler
UMC 28HPC process standard synchronous high density TCAM memory compiler
UMC 40nm LP process standard synchronous high density TCAM memory compiler.
UMC 40nm LP process standard synchronous high density TCAM memory compiler.
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
40LP High density dual port SRAM compiler with Vss booster feature
40LP High density dual port SRAM compiler with Vss booster feature
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral