The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
- Arithmetic Units
- release
- in stock
Arithmetic Unit IP cores provide hardware acceleration for core mathematical operations in modern SoC and ASIC designs.
These IP cores implement datapath functions such as multiply-accumulate, division, square root, and specialized numeric pipelines used throughout compute and signal-processing systems
This catalog allows you to compare Arithmetic Unit IP cores from leading vendors based on throughput, latency, area efficiency, and process node compatibility.
Whether you are designing DSP subsystems, AI accelerators, control systems, or high-performance datapaths, you can find the right Arithmetic Unit IP for your application.
The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
32-bit Floating-point Square-root IP Core
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard.
Parameterizable pipelined multiplier
A fixed-point Pipelined Multiplier IP Core with parameterizable of Input width, output width as well as pipeline stages
Multi-Channel Signature Calculator
IP
ZSP5000H is a programmable Vector Digital Signal Processor Core targeted for high performance Computer Vision and Image processin…
ZSP5000UL is a programmable Vector Digital Signal Processor Core for high performance computer vision and image processing applic…
ZSP5000 is a programmable Vector Digital Signal Processor Core for high performance computer vision and image processing applicat…
ZSPNano+ is a small, energy efficient, Digital Signal Processor Core for high performance Voice/Audio/Wireless applications.
Key Value Store/Exact Match Search Engine
The Ultra-Low-Latency (ULL) Exact Match Search Engine (EMSE) IP is latency-optimized Key-Value Store (KVS) system for Accelerated…
Power and area optimised Bitcoin miner engine
The eSi-BTC core is a Bitcoin miner engine that perform double SHA256 Hash.
ATAN_X calculates the inverse tangent of a fraction.
PIPE_SQRT is a pipelined square-root with configurable data width.
PIPE_DIV is a pipelined divider with configurable data width.
Pipelined Multiplier with generic width and depth
PIPE_MULT is a general purpose multiplier with a configurable data width and configurable number of pipeline stages.
COS_X calculates the cosine of an angle in radians.
The 18-bit Pipeline DSP slice IP Core provides the best utilization of device resources like memory, I/O, processor and clock.
Floating-point to Fixed-point Converter
Converts 32-bit floating-point numbers to fixed-point representation.
Fixed-point to 32-bit floating-point converter
FIXED_TO_IEEE is a high-speed fully pipelined conversion unit that accepts a signed fixed-point number as input and generates a 3…
32-bit Floating-point Divider IP Core
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.