Pipelined Square Root

PIPE_SQRT is a pipelined square-root with configurable data width. The design is fully scalable and modular permitting the user to specify large bit widths without compromising maximum attainable clock speed.

The function accepts input values as unsigned integers whose width is specified by the parameter dw. The output result also contains dw bits and is separated into an integer part and fractional part each of dw/2 bits wide.

• Synthesizable, technology independent VHDL Core
• Function f(x) = √x
• Input and output values as unsigned integers
• Configurable data width
• Unsigned N-bit input generates a result with N/2 integer bits and N/2 fraction bits
• Precision to within 1/2(N/2)
• High-speed fully pipelined architecture with configurable number of register stages for area/speed trade off
• One output result per clock-cycle (i.e. pipelined operation)
• Capable of clock speeds of 250MHz+ on even basic FPGA platforms
• Basic building block in digital processing functions
• Square root of integers and fixed-point numbers1
• Magnitude calculation of complex signals in digital communications systems

• Basic building block in digital processing functions
• Square root of integers and fixed-point numbers1
• Magnitude calculation of complex signals in digital communications systems