PIPE_DIV is a pipelined divider with configurable data width. The design is fully scalable and modular permitting the user to specify large dividers without compromising maximum attainable clock-speed.
The divider accepts input values as either signed or unsigned integers depending on the generic setting use_signed. An n-bit numerator and denominator will generate an n-bit result for the quotient and an n-bit result for the remainder. The output remainder always takes the sign of the numerator and is determined by the formula:
Rmd = Num − Quo ∗ Den
Where Rmd, Num, Quo and Den represent the remainder, numerator, quotient and denominator respectively.
In the case of a divide by zero, then the div_zero flag is asserted at the divider output and the maximum value possible is returned in the quotient. The remainder takes the value of the numerator. For example, if dw = 8, the division -3/0 will return a result of -128 for the quotient and -3 for the remainder. The division 3/0 would return a remainder of 3 and a quotient of 127 for signed arithmetic or 255 for unsigned.
Values are sampled on the rising clock-edge of clk when en is high. The number of register stages in the pipeline may be modified in order to trade off maximum speed against the total resource used. The overall pipeline latency of the divider is given by the formula:
Latency=dw / reg_stages
For example, a 24-bit divider with the number of register stages set to 3 will result in a circuit with 8 clock cycles of latency. In other words, the result of a division will take 8 clock-cycles to appear at the output. Note that while the latency may change depending on the implementation, the throughput is always maintained at one output result per clock.
