Survey shows SoC design data management is mission critical
Shiv Sikand, IC Manage
EETimes (10/22/2010 12:02 PM EDT)
Nearly half (47 percent) of IC design engineering and CAD management indicated that design data management issues had caused design and tapeout delays for their organizations. The average delay cited was almost 3 workweeks (14 days).
This is one of the findings of a blind, worldwide survey of 426 IC design professionals on Global SoC Design Management. The majority of the respondents (53 percent) held engineering and CAD management positions. The remaining respondents included digital, full custom and FPGA designers (32 percent), verification engineers (8 percent), and software and firmware developers (7 percent).
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related Articles
- System-on-chip (SoC) design is all about IP management
- Evaluating Data Management Software
- Take control of design data management
- Standardizing data interchanges among design tools in the ECU development process: Pt. 1 - Models, formats, and data management
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection