Survey shows SoC design data management is mission critical
Shiv Sikand, IC Manage
EETimes (10/22/2010 12:02 PM EDT)
Nearly half (47 percent) of IC design engineering and CAD management indicated that design data management issues had caused design and tapeout delays for their organizations. The average delay cited was almost 3 workweeks (14 days).
This is one of the findings of a blind, worldwide survey of 426 IC design professionals on Global SoC Design Management. The majority of the respondents (53 percent) held engineering and CAD management positions. The remaining respondents included digital, full custom and FPGA designers (32 percent), verification engineers (8 percent), and software and firmware developers (7 percent).
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- System-on-chip (SoC) design is all about IP management
- Evaluating Data Management Software
- Take control of design data management
- Standardizing data interchanges among design tools in the ECU development process: Pt. 1 - Models, formats, and data management
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems