Scenario Coverage In Formal Verification

A rapid increase in complexity with heterogeneous assemblies and advanced-node chips is raising all sorts of questions on the formal verification side about the completeness of coverage. Engineers may assume proofs are complete, but in many cases they're black boxes that provide little or no insights into what's actually being proven. This is where scenario coverage comes into play. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about the need for quantitative metrics and qualitative completeness, showing which stimuli are reachable, whether the overall intent of the design is properly expressed — and equally important, which scenarios were not proven.