VLIW on AMBA
VLIW on AMBA
By David Larner, Embedded Systems
August 23, 2001 (11:45 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010823S0030
Siroyan is to deploy ARM's open standard Advanced Microcontroller Bus Architecture (AMBA), both in its first synthesisable core (a “soft core”) - code-named Rubicon and its first test chip - code-named Spey. The test chip will be manufactured later this year on UMC's 0.15micron process. Siroyan's processor uses a very long instruction word (VLIW) architecture -- code-named Opus. This combines scalable high-performance DSP and RISC functionality in a single core, together with memory management elements.
Related Semiconductor IP
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
Related News
- HP helps put VLIW into STMicro's system-chip
- STMicro readies Bluetooth SoC, VLIW cores
- Coreum Technology, Inc. Licenses TriMedia[tm] TM32[tm] VLIW Processor Core
- Low-cost embedded VLIW platform under construction
Latest News
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Vayavya Labs and Tenstorrent Partner to Accelerate RISC-V Hardware and Software Development Through Virtual Platform Modeling
- RaiderChip’s Edge NPU reaches more than 50 Generative AI Models with the addition of Qwen3.8-27B