TSMC Creates Design Options for New 3nm Node
By Alan Patterson, EETimes (June 22, 2022)
Taiwan Semiconductor Manufacturing Co. (TSMC) has created versions of its upcoming 3nm FinFET node that’s ramping up later this year, allowing chip designers to enhance performance, power efficiency, and transistor density — or select a balance of those options.
TSMC’s 3nm technology, starting production later in 2022, will feature the company’s FinFlex architecture offering choices of standard cells with a 3–2 fin configuration for performance, a 2–1 fin configuration for power efficiency and transistor density, or a 2–2 fin configuration for efficient performance.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 3.3V Capable GPIO on TSMC 28nm RF HPC+
- 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- LDO Voltage Regulator, 250 mA, TSMC N3P
- LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
Related News
- A closer look at TSMC's 3-nm node and FinFlex technology
- TSMC Expansion in Arizona to Target 3-nm Node
- GUC Announces Successful Launch of Industry's First 32G UCIe Silicon on TSMC 3nm and CoWoS Technology
- Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium
Latest News
- Europe’s Chip Industry: Perfect Storm or Perfect Timing?
- Skymizer and MiTAC Computing to Showcase a 2.8-Trillion-Parameter AI Model Running on a Single Air-Cooled Server at SC26
- Arteris Announces Financial Results for the Third Quarter and Estimated Fourth Quarter and Updated Full Year 2026 Guidance
- AccelerComm Partners With Tier-1 Mobile Network Operator to Pioneer AI-Controlled Energy Consumption in 5G Networks
- proteanTecs Appoints Head of Cadence Japan Toshifumi Kaneko to Advisory Board