TSMC plans 3-D IC assembly launch early in 2013
Peter Clarke, EETimes
2/2/2012 8:32 AM EST
LONDON – Leading IC foundry Taiwan Semiconductor Manufacturing Co. Ltd. plans to announce 3-D IC assembly service as a general offering at the beginning of 2013, according to Maria Marced, president of TSMC Europe.
The technology is called COWOS internally, standing for chip on wafer on substrate and Marced said the company has one year to get all physical design kits and EDA support in place to allow customers to design with COWOS.
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