Transceiver IP core
Transceiver IP core
By
January 6, 2002 (10:42 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011203S0011
LaSer is a is a 10/40-Gbps serial transceiver IP block designed specifically for InfiniBand, SONET, and 10 Gigabit Ethernet chip designs. The IP core is available in quad, octal, and 16-channel configurations. It is currently being implemented in 0.18-ìm, 0.15-μm, and 0.13-μm processes from UMC and other foundries. Leda Systems, www.ledasystems.com
Related Semiconductor IP
- GPU
- V-by-One Verification IP
- AI model compression IP
- Hardware compressed memory IP for CXL devices and chip-to-chip links
- Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Related News
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- TES Launches 3.3 V CAN Transceiver IP for Single‑Chip Solutions
- CAST Introduces Microsecond Channel Controller IP Core for Automotive Power and Sensor Interfaces
Latest News
- TSMC Boosts 2026 Expansion Budget, Adds $100B to U.S. Investment
- ZeroPoint Technologies Announces ZeroStream
- TSMC Reports Second Quarter EPS of NT$27.25
- Rapidus and Cadence Partner on Agentic AI for Advanced SoC Design
- Defacto’s SoC Compiler Drastically Improved Productivity of L&T Semiconductor Technologies