Kerala Positions Design and IP at Core of Chip Strategy
By Yashasvini Razdan, EETimes | November 4, 2025

Kochi, Kerala — While Gujarat boasts about OSATs and fabs, the Indian state of Kerala is charting a different path with its design-first semiconductor roadmap that focuses on chip design, testing and IP creation rather than competing to build multi-billion-dollar fabs.
Unveiling the state’s Vision 2031 framework at ReCode Kerala 2025, Chief Minister Pinarayi Vijayan said Kerala aims to create half a million jobs in the IT sector within the state itself, capture 10% of India’s IT market share and grow the sector’s economic output to ₹4.41 trillion (about $49.7 billion) by 2031.
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