Paradigm Works Announces VMM 1.0 enhancements to its SystemVerilog FrameWorks VMM Template Generator software
Andover, MA -- May 4, 2009 --
Paradigm Works, Inc., a world-class leader in ASIC and FPGA technology and development services, today announced VMM 1.0 enhancements to its SystemVerilog FrameWorks™ VMM Template Generator software. The VMM Template Generator takes user input parameters and automatically creates a functional framework for an VMM compliant verification environment. Today's release includes enhanced features such as:
- Integration with VMM Open Source Library
- User Defined Base Class Support
- Runs on Both VCS and Questa
- Best Practice VIP Structure for Easy Customization and Reuse
- Testbench with Scoreboard Wrapper and Shutdown Manager Wrapper for Maximum Reusability
- User Guide to Assist Customization of the Generated Testbench
Verification teams at all experience levels will find that this tool enables the rapid adoption, implementation and the consistent scaling of the VMM methodology across team and corporate boundaries. Teams with technical leadership concentrated in one or a few geographical locations will find the VMM Template Generator particularly useful for scaling their expertise and ensuring consistency across physically distinct sites and individuals with varying degrees of expertise.
The SystemVerilog FrameWorks™ VMM Template Generator is available for free! Click here to create your VMM environment!
Coming Soon!
- VMM 1.1 Support!
- Release as an Open Source package via SourceForge.net!
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- SystemVerilog FrameWorks VMM Template Generator Upgraded for VMM 1.1
- Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM
- eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool
- Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options