Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM
Andover, MA, June 09, 2010 — Paradigm Works, a world-class leader in ASIC and FPGA software and development services, today announced that its SystemVerilog FrameWorks™ Template Generator software now supports UVM (Universal Verification Methodology).
The UVM Template Generator takes user input parameters and automatically creates a functional framework for a UVM-compliant verification environment. The current UVM Template Generator release is compatible with UVM 1.0 EA (Early Adopter).
Visit the Paradigm Works Download Page to customize, create, and download a framework UVM environment.
Visit UVM World for additional information on the UVM or to download the UVM kit.
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related News
- Paradigm Works Announces VMM 1.0 enhancements to its SystemVerilog FrameWorks VMM Template Generator software
- SystemVerilog FrameWorks VMM Template Generator Upgraded for VMM 1.1
- eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool
- Agnisys Offers Free Register Generator for UVM
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA