Silicon Hive announces two new Avispa processors
June 22, 2005
-- Silicon Hive has announced two new cores in the award-winning Avispa family. The new cores are the Avispa CH1 processor, a very high performance, programmable inner-receiver processor optimised for OFDM systems; and the Avispa IM1 processor, a fairly-general, high-performance, low-cost VLIW processor ideal for printing and imaging applications. Both cores are available immediately for licensing. The core's datasheets are available for downloading below:
- Avispa CH1 Datasheet
- Avispa IM1 Datasheet
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- Silicon Hive Licenses Avispa Processor to Agere Systems
- NXP Ramps Automotive Processing Innovation with Two Processors on TSMC 16nm FinFET Technology
- Philips' Silicon Hive to develop IP cores
- Silicon Hive introduces fully validated reconfigurable processor solutions for software defined radio
Latest News
- Cadence Wins Five 2026 TSMC OIP Partner of the Year Awards
- Lattice Delivers Industry-First PQC-Enabled Platform Firmware Resilience for AI Infrastructure with Lattice Sentry Solution Stack
- AI agents are changing what CPU performance means
- intoPIX to Demonstrate JPEG XS, IPMX and SMPTE ST 2110 Solutions at NAB Show New York 2026
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI