Silicon Hive announces two new Avispa processors
June 22, 2005
-- Silicon Hive has announced two new cores in the award-winning Avispa family. The new cores are the Avispa CH1 processor, a very high performance, programmable inner-receiver processor optimised for OFDM systems; and the Avispa IM1 processor, a fairly-general, high-performance, low-cost VLIW processor ideal for printing and imaging applications. Both cores are available immediately for licensing. The core's datasheets are available for downloading below:
- Avispa CH1 Datasheet
- Avispa IM1 Datasheet
Related Semiconductor IP
- 1.6T Ultra Ethernet Controller
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
Related News
- Silicon Hive Licenses Avispa Processor to Agere Systems
- NXP Ramps Automotive Processing Innovation with Two Processors on TSMC 16nm FinFET Technology
- Philips' Silicon Hive to develop IP cores
- Silicon Hive introduces fully validated reconfigurable processor solutions for software defined radio
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA