€270m for RISC-V chiplets to build European exascale supercomputers
By Nick Flaherty, eeNews Europe
A Framework Partnership Agreement (FPA) aims to set up a long term partnership between the EuroHPC joint undertaking and a consortium of industry, research organisations and the institutions in High Performance Computing. This would drive a ‘strategic and ambitious R&D initiative contributing to the development of innovative HPC hardware and software technology based on the open RISC-V ecosystem’.
This will be followed by a plan to build and deploy exascale and post-exascale supercomputers based on the technology.
To read the full article, click here
Related Semiconductor IP
- RISC-V Display Connectivity Subsystem (DCS)
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
Related News
- Hewlett Packard Enterprise and SiPearl Partner to Develop HPC Solutions with European Processors and Accelerate Europe's Adoption of Exascale Supercomputers
- Launch of SiPearl, designing the microprocessor for the European exascale supercomputer
- European Processor Initiative partner SiPearl will provide its general purpose processor for Europe's first EuroHPC exascale supercomputer JUPITER
- Momentum Builds on RISC-V European Adoption
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA