Why RISC-V + Blockchain Is the Conversation I’ve Been Waiting to Have
By Daniela Barbosa, GM of Decentralized Technologies at the Linux Foundation & Executive Director, LF Decentralized Trust
EETimes | October 14, 2025
The open RISC-V ISA has always been about freedom and flexibility in hardware design. Now a compelling new use case gives developers a software-only abstraction layer, taking privacy and flexibility to new heights.

There are rarely moments in technology when two open ecosystems simply ‘click’ into place. Yet here I am, feeling like the officiant between two such entities: the open hardware standard RISC-V, and the shared, immutable digital ledger that is blockchain.
Blockchain is no longer an experiment or a buzzword; it’s becoming part of the world’s critical infrastructure.
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