Release of Post-Quantum Cryptographic Standards Is Imminent
By Robert Huntley, EETimes Europe (July 23, 2024)
EE Times Europe caught up with Joppe Bos, a cryptographic researcher at NXP Semiconductors and co-author of one of the selected algorithms, to learn the current status of the standardization process.
As the quantum computing industry advances and the possibility of large-scale fault-tolerant quantum computing becomes ever nearer, post-quantum cryptography (PQC) is paramount. Cybersecurity professionals eagerly await the publication of the selected algorithm standards by the U.S. National Institute of Standards and Technology (NIST), which are in the final stages of industry consultations and ratification. Starting in 2016, NIST has been instrumental in leading global efforts to define cryptographic algorithms capable of resisting brute-force attempts by quantum computers to compromise them.
EE Times Europe caught up with Joppe Bos, a cryptographic researcher at NXP Semiconductors and co-author of one of the selected algorithms, to learn the current status of the standardization process.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related News
- Crypto Quantique announces first post-quantum computing IoT security platform compliant with new NIST standards
- NIST Releases First 3 Finalized Post-Quantum Encryption Standards
- zeroRISC Successfully Implements Post-Quantum Cryptographic Algorithm for Firmware Signing in Chip Provisioning Platform
- KiviCore and CAST Release Post-Quantum Cryptographic Key Encapsulation IP Core
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA