Pine64 launches world's first RISC-V tablet device - PineTab-V for presale
World's first t RISC-V tablet device - PineTab-V is announced as available for pre-order.
April 14, 2023 -- PineTab-V is designed by the worlding leading hardware manufacturer Pine64. The tablet carries StarFive JH7110 as the primary SoC processor.
PineTab-V features a 1200×800 10.1” IPS LCD panel with wide viewing angles, a sturdy metal chassis, two USB-C ports (1x USB 3.0, 1x USB 2.0 with charging), a digital video out port, a front 2MPx and rear 5MPx camera as well as a 6000mAh battery. The tablet comes bundled with a magnetically fitted detachable backlit keyboard (connecting via pogo pins using USB 2.0 protocol) that doubles up as a carry case and is available in two hardware configurations:
- 4GB LPDDR4 RAM / 64GB eMMC flash storage - $159.99 - Purchase Link: https://pine64.com/product/pinetab-v-10-1-4gb-64gb-risc-v-based-linux-tablet-with-detached-backlit-keyboard/
- 8GB LPDDR4 RAM / 128GB eMMC 5.1 flash storage - $209.99 - Purchase Link: https://pine64.com/product/pinetab-v-10-1-8gb-128gb-risc-v-based-linux-tablet-with-detached-backlit-keyboard/
The following figure shows the motherboard of the tablet:
Pine64 defines the tablet as a device for development purposes only, the device works as a convenient development platform targeted at the developers who are interested in bringing Linux support to JH7110 and, by extension, the entire RISC-V ecosystem.
As the world's first mass-produced RISC-V multimedia processor, this time, JH7110 is used as the main control SoC for PineTab-V. This will definitely be a remarkable milestone for promoting the application of RISC-V processors in high-end business scenarios.
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related News
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers
- S2C Named Andes Technology’s 2026 Partner of the Year
- Fraunhofer RISC-V Secure Element Accelerates Secure Chip Development After Successful Silicon Validation
Latest News
- JEDEC® Publishes First Industry-Wide Silicon Photonics Reliability Standard for AI, Datacenter and Telecom Infrastructure
- Orthogone Technologies Launches Ultra-Low-Latency FPGA IP Portfolio for Multi-Industry Deterministic Networking
- TIER IV joins Arm Total Design for Physical AI to accelerate ready-to-use Autoware solutions through Open AD Kit
- SEMIFIVE Signs Turnkey Contract with Mobilint to Develop Robotics AI Chip Under 'K-On-Device AI Semiconductor' Program
- ICTK to Acquire Network Security Firm withnetworks, Expanding from Security Chips into Global Enterprise Security Solutions