Open-source core implements MD5 cryptography

Open-source core implements MD5 cryptography
By Richard Goering, EE Times
July 22, 2003 (2:45 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030722S0036

SANTA CRUZ, Calif. — Providing a cryptography solution for systems-on-chip, a design and verification engineer has developed an open-source core that implements the MD5 message digest algorithm. The author, Swapnajit Mittra, runs Project Veripage, a free Web resource for Verilog Programming Language Interface (PLI) users.

The core, Pancham, is available for downloading under the GNU Public License. Although Pancham has its own Web page, part of the intent is to establish Project Veripage as a source for intellectual property (IP) cores, Mittra said.

MD5 is widely used in secured communications devices for applications such as keyed authentication, Mittra said. Although there are open-source cores for other encryption algorithms, Pancham, which means "fifth" in Sanskrit, is the first open-source MD5 core, he said.

"Cryptographic cores are quick ly becoming popular," Mittra said. "My hope is that Pancham will further help popularize crypto cores."

The MD5 algorithm takes in a message of arbitrary length, and produces a fixed 128-integer "fingerprint" of the message. A set of four 32-bit "salt" values initializes the internal data structure. "It's a method for verifying data integrity that is more reliable than checksum or similar methods," Mittra said.

Pancham is written in synthesizable Verilog code, and comes with a test bench. Mittra said the core is approximately 27,000 gates. Users are invited to report bugs to the Pancham Web site, and patches for bugs are welcome.

Mittra founded Project Veripage in 1996 to provide a free Web resource for Verilog PLI users. He has also developed a demo version of a Camellia crypto core, and has created Decodify, an open-source tool that reveals the individual signal value of a bus. Mittra is the author of the book "Principles of Verilog PLI" and chairma n of Accellera's SystemVerilog C/C++ committee.