Olympus adopts DMP's Hybrid Graphics IP core for OLYMPUS OM-D E-M1
Tokyo, Japan, January 30, 2014 -- Digital Media Professionals Inc. (DMP), a leading provider of 2D/3D graphics IP (Intellectual Property) cores, announced today that Olympus, a Japan based manufacturer of optics and reprography products , has selected DMP 2D/3D hybrid graphics IP core “SMAPH-H” for their OLYMPUS OM-D E-M1, the flagship model of a mirrorless system, integrating DSLR.
SMAPH-H is a hybrid graphics IP core optimized for high-performance, high-quality user interfaces and mobile applications, supporting OpenVG 1.1 and OpenGL ES 1.1/2.0 APIs. Vector and 3D graphics can share hardware components without any loss of graphics rendering performance. This IP core successfully reduces both die size and power consumption.
“We are really honored to be building on our close relationship with Olympus and we are excited that Olympus has selected SMAPH-H for its new flagship model of mirrorless interchangeable-lens cameras. The flexibility of the DMP graphics solution is well suited to support Olympus’s evolving needs as it continues to enhance its product lines with graphics functionality.” – Tatsuo Yamamoto, CEO, DMP.

About DMP
Digital Media Professionals Inc. (TOKYO: 3652) develops industry leading 2D and 3D graphics solutions for global consumer electronics, mobile, embedded and automotive markets. The company was founded in Tokyo, Japan in 2002 and is currently developing several graphics IP cores based on the Khronos™ Group open standards and DMP’s cutting edge 3D graphics IP “Maestro Technology”.
Related Semiconductor IP
- GPU
- PowerVR Automotive XS GPU
- E-Series GPU IP
- High performance GPU for cloud gaming with DirectX support
- Arm’s flagship GPU providing ultimate mobile gaming experiences
Related News
- DMP 3D Graphics IP Core "PICA200 Lite" is adopted for OLYMPUS Tough TG-1
- DMP 3D Graphics IP Core "PICA200 Lite" is adopted for OLYMPUS PEN Lite E-PL5.OLYMPUS PEN mini E-PM2
- TES offers PKCS IP Core for System-on-Chip (SoC) Designs
- Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
Latest News
- Silvaco Announces Partnership with Dassault Systèmes to Advance First-Time-Right Semiconductor Manufacturing
- Socionext Broadens SoC Roadmap with Intel 18A-P Process Technology
- BrainChip and Neuromorphyx Announce an AKD1500 Embedded Developer Board, Bringing Neuromorphic AI to the Embedded Engineering Community
- M31 Reports Nearly Fourfold Growth in Advanced-Node Royalties as Long-Term Investments Begin to Bear Fruit
- Andes Technology’s D23-SE RISC-V Processor Achieves ISO 26262 ASIL‑B and ASIL‑D Certification for Functional Safety Applications