MIPS plans tool additions to close compiler gap
MIPS plans tool additions to close compiler gap
By Chris Edwards, EE Times UK
March 5, 2002 (1:22 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020303S0005
MIPS Technologies plans to extend its work in software tools to help close the gap between the compiler and processor core technology. But the company is to stick with its model of not selling tools directly and will work with third parties. The model being used by MIPS is similar to that used by Intel to get support for its MMX and later instruction set extensions from third-party compilers. Intel licenses technology to the tool vendors. ARM Holdings, MIPS' main competitor, takes the approach of owning a full tool chain. Proposed extensions to the MIPS architecture will complicate the job of compiler writers. In response, the company is to write more software components to ensure that the compilers have the necessary optimisations available. Keith Diefendorff, vice-president of product strategy for MIPS, said: "There are critical pieces of software that MIPS has to invest in." Kevin Meyer, vice-president of marketing, added: & quot;They will be building blocks, not value-added software. We do some software development today. Our simulator is integrated into GreenHills' toolchain. Going forward, we will provide blocks ourselves to build optimised solutions." Diefendorff said: "If we don't make sure the enabling [software] technologies are in place, there is no sense in building high-performance cores."
Related Semiconductor IP
- AI model compression IP
- Hardware compressed memory IP for CXL devices and chip-to-chip links
- Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
- LZ4-compatible hardware compressor and decompressor IP
- Ultra-low jitter, high SFDR LC-based PLL-12.5GHz
Related News
- SoC Standards Leader VSI Alliance Announces Plans to Close Operations
- Green Hills Software and Imagination Report Expanded Compiler and Tools Support for MIPS CPUs
- Siemens leverages AI to close industry’s IC verification productivity gap in new Questa One smart verification solution
- Arteris Bridges Hardware-Software Gap with New EDA Tool
Latest News
- TSMC Boosts 2026 Expansion Budget, Adds $100B to U.S. Investment
- ZeroPoint Technologies Announces ZeroStream
- TSMC Reports Second Quarter EPS of NT$27.25
- Rapidus and Cadence Partner on Agentic AI for Advanced SoC Design
- Defacto’s SoC Compiler Drastically Improved Productivity of L&T Semiconductor Technologies