IMEC proposes three memories for embedded RAM

Peter Clarke
(07/13/2004 10:21 AM EDT)

  SAN FRANCISCO — The Belgian research institute IMEC has invited companies and other research centers to participate in a collaborative research program on novel memories for embedded RAM. IMEC claimed that its expertise with the three memory types and relevant materials would allow the program to generate useful results within six to 18 months.

IMEC (Leuven, Belgium) is proposing three novel forms of memory architecture for research, targeted at second and higher levels of on-chip cache memory to be implemented in the 45-nm manufacturing node and below.

The three memory types are: direct tunneling RAM; a ferroelectric field effect transistor; and an silicon-on-insulator (SOI) floating body cell. The three concepts will be implemented in silicon by the end of 2004 to demonstrate their feasibility, IMEC said.

The direct-tunneling RAM uses a 1.5-nm thick oxide flash memory structure in which the charge can be stored on either a floating gate or on a charge-trapping layer. In both cases, the use of high-k materials is being considered to lower the write/erase voltages. First simulation results showed the possibility of a 10-ns programming time at the 45-nm node.

IMEC is again proposing the use of high-k materials within the ferroelectric field effect transistor, a memory that is different to the capacitor-based ferroelectric RAM.

The floating body cell is a memory effect in SOI devices initially developed at IMEC in 1988, the organization said. The technology is now being adapted for planar as well as FinFET device structures.