Hidden IP: booby trap or buried treasure?
George Leopold, EE Times
(04/30/2007 9:00 AM EDT)
WASHINGTON — If the process by which technology standards are forged and implemented isn't broken, it is surely straining under the weight of globalization, relentless technological change, patent-infringement and antitrust lawsuits as well as increasingly noisy standards battles among competing industry consortia.
In response, standards bodies are reviewing their procedures for dealing with intellectual-property (IP) rights. Many are focusing on patent and licensing disclosure. The IEEE, for instance, is awaiting a government opinion on a plan to use voluntary patent disclosure in its standards proceedings (see story, below). Groups like VITA, the Digital Video Broadcasting Project and Jedec are either conducting similar reviews or contem- plating new disclosure requirements.
(04/30/2007 9:00 AM EDT)
WASHINGTON — If the process by which technology standards are forged and implemented isn't broken, it is surely straining under the weight of globalization, relentless technological change, patent-infringement and antitrust lawsuits as well as increasingly noisy standards battles among competing industry consortia.
In response, standards bodies are reviewing their procedures for dealing with intellectual-property (IP) rights. Many are focusing on patent and licensing disclosure. The IEEE, for instance, is awaiting a government opinion on a plan to use voluntary patent disclosure in its standards proceedings (see story, below). Groups like VITA, the Digital Video Broadcasting Project and Jedec are either conducting similar reviews or contem- plating new disclosure requirements.
To read the full article, click here
Related Semiconductor IP
- Adaptive Voltage Scaling (AVS) Bus Target IP
- Adaptive Voltage Scaling (AVS) Bus Host Controller
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Related News
- CAST Launches Multimedia Line with IP Cores for Image or Video Compression
- ARC International Next-Generation SoC Development Platform Targets “Six Months or Less” Design Cycle
- Xelic Announces Frame Mapped Generic Framing Procedure Core Availability for Integration into ASIC or FPGA Networking Applications
- Sarnoff Silicon IP For VSB/QAM Demodulation Lets TV Sets Receive Cable or Broadcast Digital/HDTV
Latest News
- Andes Technology and Mirabilis Design Announce Collaboration on System-Level Models for Andes RISC-V Processor IP
- Synopsys Advances Agentic AI Chip Design with AMD and Microsoft
- Synopsys and Intel Foundry Fast-Track Customer Readiness from Silicon to Systems on Intel 14A
- Samsung Electronics and Broadcom Expand Strategic Collaboration Across Memory and Foundry Technologies
- NVIDIA Expands NVIDIA Agent Toolkit With NVIDIA PhysicsNeMo and CUDA-X Libraries to Transform How the World Engineers, Designs and Builds