Electronics enters era of 'systemic risk'
Rick Merritt, EETimes
8/30/2011 7:36 PM EDT
"We're not just dealing with silicon scaling complexity but with a kind of systemic complexity where being best-in-class in one area is not sufficient to avoid risk and risks are going up," said Aart de Geus, chief executive of Synopsys in a panel at the annual GlobalFoundries conference here.
To read the full article, click here
Related Semiconductor IP
- Dual Channel 8b D/A Converter - TSMC T40ULP
- Dual Channel 12b D/A Converter - TSMC T40ULP+ESF3
- 8bit D/A Converter - TSMC 22nm ULP
- 12bit 2MSps A/D Converter - TSMC T22ULP
- TSMC 2nm 1V2 GPIO
Related News
- Samsung Electronics Unveils Foundry Vision in the AI Era at Samsung Foundry Forum 2023
- Codesign tools aren't ready yet for SoC era
- Embedded designs flood Microprocessor Forum for 'post-PC' era
- ATE vendors cozy up to on-chip test for SoC era
Latest News
- Brite Semiconductor Releases 28nm High-Performance SAR ADC IP, Driving Upgrades for High-Speed Signal Chain Applications
- Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure
- BrainChip Launches Symphony Community Akida Bundle For IBM’s Workload Management Solution
- StarIC Appoints Dr. Masum Hossain as Chief Technology Officer
- Andes Technology Empowers RISC-V Developers with Its New Streamlined IDE, RVBuilder