Electronics enters era of 'systemic risk'
Rick Merritt, EETimes
8/30/2011 7:36 PM EDT
"We're not just dealing with silicon scaling complexity but with a kind of systemic complexity where being best-in-class in one area is not sufficient to avoid risk and risks are going up," said Aart de Geus, chief executive of Synopsys in a panel at the annual GlobalFoundries conference here.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- Samsung Electronics Unveils Foundry Vision in the AI Era at Samsung Foundry Forum 2023
- Codesign tools aren't ready yet for SoC era
- Embedded designs flood Microprocessor Forum for 'post-PC' era
- ATE vendors cozy up to on-chip test for SoC era
Latest News
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools