DeepX Hints At Next-Gen AI Chips
By Sally Ward-Foxton, EETimes (August 30, 2024)
SANTA CLARA, Calif.—DeepX demonstrated its two first-generation chips, which are aimed at different markets, at the Embedded Vision Summit, and gave EE Times some hints on its next-generation chip for AI on-device and in autonomous robots.
Demos
The V1 (previously named L1) is an SoC with the DeepX 5-TOPS NPU alongside quad-RISC-V CPUs. It also features a 12-MP image signal processor (ISP). This is a small, sub-$10 SoC for edge devices, built on Samsung 28-nm process technology for power efficiency. DeepX’s V1 demo runs YOLO v7 at 30fps for real-time processing. Its power envelope is 1-2 W.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related News
- When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform
- Axelera AI and Andes Technology Partner to Power Next-Generation “Europa” AI Platform with High-Performance RISC-V AX65 Cores
- NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
- RISC-V Targets Data Centers, Edge AI, Space
Latest News
- Year-to-Date Global Semiconductor Sales Top $1 Trillion Through August
- Xiphera launches nQrux® Root of Trust with Post-Quantum Cryptography
- Skyechip Joins Rapidus Core Ecosystem, Bringing Advanced Silicon IP For AI and HPC to Japan's 2nm Platform
- GUC Monthly Sales Report – September 2026
- Rapidus Unveils “Rapidus CORE”, New Global Ecosystem Framework Supporting the Development and Mass Production of Cutting-Edge Semiconductors