DeepX Hints At Next-Gen AI Chips
By Sally Ward-Foxton, EETimes (August 30, 2024)
Demos
The V1 (previously named L1) is an SoC with the DeepX 5-TOPS NPU alongside quad-RISC-V CPUs. It also features a 12-MP image signal processor (ISP). This is a small, sub-$10 SoC for edge devices, built on Samsung 28-nm process technology for power efficiency. DeepX’s V1 demo runs YOLO v7 at 30fps for real-time processing. Its power envelope is 1-2 W.
To read the full article, click here
Related Semiconductor IP
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Tiny, Ultra-Low-Power Embedded RISC-V Processor
Related News
- Cassia.ai Achieves Breakthrough in AI Accelerator Technology with Successful Tapeout of two Test Chips
- MIPS S8200 Delivers Software-First RISC-V NPU To Enable Physical AI at the Autonomous Edge
- Quadric, Inference Engine for On-Device AI Chips, Raises $30M Series C as Design Wins Accelerate Across Edge
- SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink™ Fusion
Latest News
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite
- Mosaic SoC raises $3.8M to bring real-time spatial intelligence to every consumer device
- UMC Reports First Quarter 2026 Results
- Rambus Appoints Sumeet Gagneja as Chief Financial Officer
- SEMI Reports Worldwide Silicon Wafer Shipments Increase 13% Year-on-Year in Q1 2026