China forms its own chiplet standard amid isolation
By Peter Clarke, eeNews Analog (March 27, 2023)
The China Chiplet Industry Alliance has released the ‘Chiplet Interconnection Interface Standard’ known as ACC1.0, according to the Financial Association Press.
The standard defines a high-speed serial port and is focused on optimization based on the domestic packaging and substrate supply chain, with cost and commercial practicality as a key consideration, the report said. The standard was developed by the Cross Information Core Technology Research Institute working with the China Chiplet Industry Alliance, which includes domestic system, IP, and packaging manufacturers.
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