Certus Semiconductor releases I/O library in TowerJazz's 65nm process

September 25, 2024 -- Certus is excited to announce that its 1.2V/3.3V wire-bond I/O library in TowerJazz’s 65nm process is silicon-verified, and exceeding expectations.This is a Foundation I/O library featuring 8kV HBM and >500V CDM ESD protection, standard, in all I/O’s and Powers, ensuring robust reliability in challenging environments. The library’s compact footprint (70x100um), crafted explicitly for space-efficient designs, makes it ideal for applications where size is critical.

The library offers a robust GPI-LVDS combo cell, with six drive strength settings and an impressive 1.2Gbps transmit and receive speeds, all contained within a footprint of two standard I/O cells (140 x100um). Additionally, to its role as a versatile LVDS TX or RX front-end, the cell can also act as two separate selectable TTL-compliant General-Purpose Inputs (GPI), which optimizes production testing efficiency.

The Library 3.3V GPIO (General Purpose Input Output) functionality supports standard LVCMOS features and frequencies up to 100MHz for transmission and 270MHz for receiving, with selectable 50kΩ/pull-up/pull-down resistors for enhanced integration flexibility.

The Library 3.3V to 5V ODIO (Open-Drain Input Output) ensures seamless compatibility with I2C protocols in both 3.3V and 5V system buses.

Supporting the digital features is a full set of 1.2V and 3.3V analog I/O’s. Also featured is an RF cell with <290fF self-capacitance (including Bondpad) and high 8kV ESD protection. If your design requires an array of fill, corner, or break cells, this library offers a flexible array of options for padring construction, accommodating diverse design goals.

Feel free to reach out to a Certus representative for more information!