Digital Blocks Introduces the DB9100 BitBLT / 2D Graphics Engine Verilog IP Core Family for Accelerated Graphics Display Applications
The DB9100 BitBLT / 2D Graphics Engine IP Core accelerates graphics development for ASIC, ASSP, & FPGA design teams, while off-loading the graphics function from the main Processor and enhancing software developer productivity.
GLEN ROCK, New Jersey, July 1, 2011 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals, Networking, Display Controller, Display Link Layer, 2D Graphics, and Audio / Video processing requirements, today announces the DB9100 BitBLT / 2D Graphics Engine synthesizable RTL Verilog IP Core family. The DB9100 Graphics Engine IP complements Digital Blocks DB9000 family of TFT LCD Controller IP Cores providing a system-level solution to graphics display applications development centered around ASIC, ASSP, & FPGA components.
The DB9100 BitBLT Graphics Engine provides 256 Raster Operations on 3 sources of frame buffer data for Block Transfers with an array of available Bitmap & 2D Graphics operations. The high performance 2D Graphics Engine renders Line, Polygon, & Polygon Block Fills.
DB9100 Family of BitBLT Graphics & 2D Graphics IP
The DB9100 family supports the AMBA AXI4, AXI, AHB, and Avalon Bus fabrics. The AXI4, AXI, & AHB fabrics support ASIC & ASSP integrated circuit design teams. The AXI4 supports Xilinx FPGAs. The Avalon supports Altera FPGAs. The DB9100 is tuned to the unique capabilities of each fabric to maximize capability & performance. Please consult Digital Blocks web site for a more information.
DB9100 Software
The DB9100 comes with a Graphics API Reference Design.
Price and Availability
The DB9100 is available immediately in synthesizable Verilog, along with a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; Fax: +1- 702-552-1905; Media Contact: info@digitalblocks.com; Sales Inquiries: info@digitalblock.com; On the Web at www.digitalblocks.com
Related Semiconductor IP
- 2D Graphics Hardware Accelerator (AXI4 Bus)
- 2D Graphics Hardware Accelerator (AHB Bus)
- 2D Graphics Hardware Accelerator (AXI Bus)
- 2D Blit and Raster Graphics
- Advanced 2D Graphics Controller
Related News
- SOC-E and SafeCore Devices to unveil a new TSN End Point IP Core: AeroTSN-EP
- CAST Introduces PSI5-HOST IP Core for Automotive Sensor Interfaces
- SoC Secure Boot Hardware Engine IP Core Now Available from CAST
- DCD-SEMI Unveils Ultra-Fast DAES IP Core for AES Encryption
Latest News
- VeriSilicon Introduces CPP2000 Camera Post-Processing IP for Embodied Robotics and Mobile Vision Applications
- Infineon opens the world's largest fab for power semiconductors and analog/mixed-signal technologies in Dresden
- Tenstorrent Sets New Performance Records, Launches TT- Ascalon S, and Expands Across Japan
- Chips&Media Signs APV codec IP Licensing Deal with North American Big Tech, Establishing the ‘Second Front’ Against Apple’s ProRes
- Chipsolve Technologies Appoints Balaji Kanigicherla as Chairman of the Board