Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process 2016-07-13 13:56:00 EDA & Design Tools
eMemory's NeoEE Solution Facilitates Module Integration for Fingerprint Applications 2016-07-13 13:28:00 IP Cores & Design
Toshiba Plans Deployment of Synopsys TetraMAX II on Upcoming SoC Design 2016-07-13 01:54:00 EDA & Design Tools
Synopsys TetraMAX II ATPG Certified for ISO 26262 Automotive Functional Safety 2016-07-13 01:50:00 EDA & Design Tools
TetraMAX II Shortens Test Pattern Generation From Days to Hours 2016-07-13 01:47:00 EDA & Design Tools
SST Announces Qualification of Embedded SuperFlash on GLOBALFOUNDRIES' BCDLite Process 2016-07-12 17:59:00 IP Cores & Design
prpl Foundation Unveils the First Open Source Hypervisor for the Internet of Things 2016-07-12 14:20:00 Misc
Microsemi Announces Imaging/Video Solution Providing a Secure, Reliable, Low Power Device for Imaging Applications 2016-07-12 14:13:00 SoC Architecture & Assembly
Chips&Media launches 2nd generation High Performance Google's VP9 and HEVC Multi-format Decoder IP 2016-07-11 16:56:00 IP Cores & Design
Renesas Adopts Cadence Interconnect Workbench to Accelerate Performance Analysis and Verification of On-Chip Interconnect 2016-07-11 16:49:00 EDA & Design Tools
AppliedMicro Adopting TSMC 7nm FinFET Process Technology 2016-07-11 15:30:00 Foundries & Process Nodes
Imec and ARM collaborate on Design-Technology Co-Optimization for 7nm technology and beyond 2016-07-11 14:11:00 EDA & Design Tools
FPGA Prototyping Becomes Even More Precise with Latest Additions to S2C's World-Class Prodigy Prototype Ready Interface Library 2016-07-11 12:22:00 Misc
Imec and Synopsys Collaborate on Interconnect Resistivity Model to Enable Early Screening of Interconnect Technology Options at Advanced Nodes 2016-07-11 06:33:00 EDA & Design Tools
IC Insights Lowers Its 2016 Semiconductor Market Forecast to -1% 2016-07-08 08:20:00 Analysis & Insight