Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It's Possible!
2019-05-29 13:17:00
Misc
Semiconductor IP News Archive - Page 458 of 1971
NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs
2019-05-28 17:20:00
EDA & Design Tools
Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development
2019-05-28 17:18:00
EDA & Design Tools
Synopsys Introduces PrimeYield for 100X Faster SoC Yield Analysis and Optimization
2019-05-28 15:10:00
EDA & Design Tools
Hex Five Adds MultiZone Security to the AdaCore Software Ecosystem
2019-05-28 09:48:00
SoC Architecture & Assembly
Sofics' clipping/scaling circuit enhances reliability of Near Field Communication (NFC) and other wireless interfaces
2019-05-28 09:29:00
Legal & IP Strategy
IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks
2019-05-28 07:13:00
EDA & Design Tools
Silvaco Announces Viola I0-X - 10X Faster I/O Pad Characterization for Nanometer Silicon
2019-05-28 04:21:00
EDA & Design Tools
TSMC to Keep Supplying Chips to Huawei
2019-05-27 12:23:00
Analysis & Insight
Faraday Showcases FinFET ASIC Solutions and SoCreative!V SoC Platform at DAC 2019
2019-05-27 10:37:00
Misc
Synopsys and Arm Collaborate to Enable Tapeouts by Early Adopters of Arm's Latest Premium Mobile Processors
2019-05-27 09:28:00
EDA & Design Tools
Cadence Full-Flow Digital and Signoff Tools Optimized for New 7nm Arm Cortex-A77 CPU
2019-05-27 09:12:00
EDA & Design Tools
Credo First to Demonstrate 7nm, 112G XSR SerDes
2019-05-27 09:06:00
Misc
Delivering next-generation AI experiences for the 5G world
2019-05-27 08:43:00
IP Cores & Design
eSilicon Technical Advisory Board Members Win Facebook Research Award
2019-05-27 03:17:00
Misc
TSMC-Certified OIP Virtual Design Environment with Synopsys Tools Now Available on Google Cloud
2019-05-23 15:23:00
EDA & Design Tools
Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs
2019-05-23 15:20:00
EDA & Design Tools
CAST Expands Popular UDP/IP Networking Cores Line
2019-05-23 12:32:00
IP Cores & Design
SmartDV Unveils First Verification IP to Support Ethernet TSN
2019-05-23 12:28:00
Verification IP
AnalogX Launches Ultra Low Power Interconnect SerDes IP Portfolio to Fuel Next-Generation I/O Connectivity
2019-05-23 10:39:00
IP Cores & Design