With SDAccel, Xilinx Embraces OpenCL
January 22, 2015
Emerging and evolving options for high-level design of FPGAs is a topic of ongoing interest at InsideDSP. Recently, for example, BDTI covered the latest version of Calypto's Catapult C-based design environment. Similarly, in August 2012 InsideDSP discussed the C-based high-level synthesis (HLS) facilities that Xilinx bundled in some versions of its Vivado FPGA design toolset. And less than a year ago, BDTI analyzed a different approach to high-level synthesis, based on the Khronos Group's OpenCL, implemented by Altera.
To read the full article, click here
Related Semiconductor IP
- Hardware Security Module (HSM) for AMD Xilinx Versal ACAP device
- Xilinx UltraScale Plus NVME Hhost IP
- Xilinx Ultra Scale NVME Host IP
- Xilinx Ultra Scale Plus SATA HOST IP
- Hardware Security Module (HSM) for Xilinx Zynq UltraScale+ MPSoC platform
Related Blogs
- PLD Overview: Xilinx and Altera
- Xilinx ARMs FPGAs, Altera to MIPSify Them
- Intel Eyeing Xilinx?
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA