Will your next ASIC ever be an FPGA?
June 14, 2012
Just over a week ago, I moderated a live webinar on EDN titled “When is an FPGA more Appropriate than an ASIC?” The participants were from Xilinx, Altera and Cadence. A repeat event was held at DAC, which I almost moderated, but because of DAC rules I was disqualified because I was also moderating the panel “Can one system model serve everybody?” Richard Goering did a nice write-up of this panel which you can find here.
So Kevin Morris performed the honors. He started by saying that we have heard this story so many times before after each new generation of FPGA is announced.
To read the full article, click here
Related Semiconductor IP
- nQrux Secure Boot
- 4K/8K Multiformat IP supporting AV2 decoder
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
Related Blogs
- Could TSMC be your next chip design cloud owner?
- Is it an ASIC? Is it an FPGA? No, it's eASIC!
- Your Car Will Never be Secure
- The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA