Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification
May 16, 2013
We have seen last week in a first post how crucial was the IP qualification process (TSMC 9000) to increase the probability of successfully Tape Out a chip. Being able to discriminate between dangerous and safe IP is the first step of TSMC 9000 Quality process, IP tagging is the complementary step, almost as essential as the first one. That’s why, for every IP or Library going through TSMC 9000, an unique IP tag is created and inserted into its GDSII stream for identification.
The IP Tag allows carrying the IP vendor information and IP denomination, and also all the quality information and production status of the specific IP or Library.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
- 32Gbps SerDes IP in TSMC 12nm FFC
- 32Gbps SerDes IP in TSMC 22nm ULP
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Blogs
- Specification Ambiguities of MIPI UniPro v1.41 clarified in MIPI UniPro v1.6
- New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP