SiFive RISC-V Proven in 5nm Silicon
OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology
Today, I am pleased to see OpenFive, a SiFive business unit that is the leading provider of customizable, silicon-focused solutions with differentiated IP, is continuing to make progress with AI design solutions with the creation of a reference design chiplet architecture using OpenFive Die-to-Die interface, OpenFive HBM3 IP subsystem, and SiFive 7-Series processor IP, for 2.5D-based SoCs. More details on the full announcement can be found on OpenFive’s announcement here, but today I want to call out the SiFive milestone of our first RISC-V processor core in 5nm.
The SiFive RISC-V-based processor portfolio is the broadest in the industry, from our upcoming SiFive Intelligence processor cores featuring RISC-V vector capabilities to area-optimized real-time cores. SiFive believes that it takes more than great processor IP to be successful in these markets by offering class-leading advanced trace and debug IP enabled by SiFive Insight. SiFive Insight is delivered pre-integrated with SiFive processor cores and gives customers the tools they need to develop sophisticated applications and is well supported by leading industry tool vendors, IAR Systems, Lauterbach, and SEGGER. Uniquely, SiFive Insight is compatible with Arm® Coresight™ to simplify the use of RISC-V in mixed-ISA environments.
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Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Blogs
- RISC-V Chiplets, Disaggregated Die, and Tiles
- RISC-V is Inevitable
- Accelerating the Future of RISC-V
- The Rapid Rise of RISC-V
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