Customization? Yes! After tape-out? Yes!

By Codasip

November 28, 2023

Another RISC-V Summit is behind us. It was a very well-attended event with many exciting talks and companies highlighting their products at the exhibition. One of the main themes was, once again, customization. Many people and companies, including Meta in their keynote, insisted on the importance of customization and how this key aspect of the RISC-V architecture enables innovation and differentiation. Because RISC-V allows customization, we can overcome problems with new demands on new architectures. The benefits of customization in the form of new instructions or microarchitecture tweaks are well known, and evidence can be found across the industry, from mobile to automotive and HPC.

As champions of Custom Compute, we, at Codasip, constantly look into new ways to get better PPAC (power, performance, area, and cost). Customization is our thing. Our combination of customizable RISC-V processor IP and design & customization automation tools has been deployed and in use for almost a decade with clear evidence of benefits.

There are cases, though, where you don’t want to freeze the choice of customization at tape-out time. For example, when the processor is part of a device with a long lifetime, it is hard to project all possible ISA extensions or other customizations. Or perhaps you would like to use the same silicon for multiple applications that need different acceleration features. How do we address such cases?

In this blog, I share with you a solution with some preliminary results that show big potential for this new approach.

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