RISC-V Cores: SweRV and ET-Maxion
December was the first RISC-V summit at the Santa Clara Convention Center. I covered that in my post RISC-V: Real Products in Volume. The one-sentence summary of the state of RISC-V is that it is already dominant in academia, and has some traction with DARPA too. I doubt any chips will be built in academia that are not RISC-V-based, and it is clear that a lot of ideas for things like hardware security will be prototyped in RISC-V. The big question is how significant it will be in the commercial world.
The big potential driver in the industry is the end of progress in general-purpose processor performance. This is a confluence of a couple of factors: the inability to increase clock rates significantly to get extra performance, and the lack of new ideas in computer architecture to increase instructions per cycle. This means that the only route to improved performance is through special-purpose CPUs that match a specialized workload (such as neural networks, or wireless modem signal processing) to specialized architectures that can do tens or even hundreds of times better.
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