Put FPGAs In Your SoCs
PORTLAND, Ore.—- Flex Logix Technologies Inc. has created a new species of product. The Mountain View, Calif. company has added field-programmable gate arrays (FPGAs) to SoCs.
Flex Logix began with a new type of FPGA based on IP from the University of California at Los Angeles (UCLA), which almost doubled the number of usable gates per chip. The new FPGAs eliminated more than 20% of the room needed for interconnect and switches, Co-Founder and CEO Geoff Tat told EE Times in an exclusive interview, and there is now nearly 50% more room for gates.
As the ARM of FPGAs, many of Flex Logix’s design blocks go next to ARM processor blocks for which they have prefab interface compatibility with ARM's busses and other architectural features. The FPGAs accelerate ARM, MIPs or any other microcontroller the customer is using. Plus they one-up the microcontroller IP suppliers by supplying both hardware and a programming environment that allows the customer to upgrade their FPGA in-the-field when new protocols, encryption algorithms, packet parsing methods or anything else comes along that requires re-configuring the embedded FPGA.
To read the full article, click here
Related Semiconductor IP
- USART Verification IP
- Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core
- VIP for Compute Express Link (CXL)
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Multi-Channel Flex DMA IP Core for PCI Express
Related Blogs
- Synopsys 10BaseT1-S VIP for your Automotive SoCs
- Using Synopsys Smart Monitors to Improve System Performance of Your Arm SoCs
- Exploring the Security Framework of RISC-V Architecture in Modern SoCs
- Addressing Challenges with FPGAs in Space Using the GR716B Microcontroller
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects