PCIe 4.0: A Quick Primer on New Features
‘Big Data’, ‘IoT’, ‘Mobile’, ‘Networking’ and ‘Storage’ applications are the key drivers for next generation high-performance systems. To meet the bandwidth requirement of the emerging applications, it was required to either increase the lane width or speed. Increasing the lane width isn’t cost effective and thus increasing speed is the best viable option. PCIe 4.0 has doubled the per lane throughput to 16GT/s, compared to 8GT/s for PCIe 3.0, delivering higher performance without increasing the lane width.
PCIe 4.0 architecture is backward compatible to previous generations of PCIe. Devices designed for previous generations will still operate correctly with the new technology. The figure below shows the evolution of PCIe specifications.
To read the full article, click here
Related Semiconductor IP
- USB-C Power Delivery IP Core
- Configurable Multi-Channel DMA Controller
- Samsung Foundry 4nm 1V8 GPIO I3C
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
Related Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
- See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+
- The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016
Latest Blogs
- The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
- From photon to actuation: How physical AI is redefining embedded compute
- Secure Boot for embedded Linux on Efinix Ti375C529: Getting started with KiviBoot-Linux
- Akida in High-Frequency Trading: The Smart Signal Layer
- Cadence Expands Sovereign AI in Europe: From Chips to AI Factories