NeuReality Accelerates 7nm AI Chip Tape-Out with Cloud-Based Emulation
Say you’re a small company with a big idea, but are just getting started. Because your first silicon AI chip design is in development, you have a limited budget to get your offering off the ground. You also know that, given competitive pressures, the faster you get to market, the better. In this scenario, any tools or technologies that can help accelerate the AI chip design and verification process can also provide a foundation for your company’s success.
For Caesarea, Israel-based NeuReality, which develops purpose-built AI inference platforms, its helping hand came by way of cloud-based chip design emulation, specifically Synopsys ZeBu® Cloud. Rather than go through the costly, time-consuming process of building its own semiconductor emulation infrastructure, NeuReality took advantage of the flexibility, scalability, and elasticity of the cloud, and achieved tape-out and production of the world’s most complex chips on schedule. Read on to learn more about NeuReality’s quest to make AI adoption easy.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Mentium Accelerates Tape-out of AI Accelerator Chip for Space Applications on Synopsys Cloud
- Leveraging a Unified Emulation and Prototyping System to Address Verification Requirements Across the Chip Development Cycle
- TetraMem Delivers RISC-V AI Accelerator Tape-Out in Record Time on Synopsys Cloud
- How Chip Startups Are Changing the Way Chips Are Designed
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing