Low-Power Design: Is the Problem Solved?
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your expectation is that the phone might go for a day before needing a recharge.” Why? Because we understand that the phone is now doing a lot more than it once did, said Wang as he entered into the main part of his talk.
We’d like to think that achieving closure on power-consumption goals during the design process is smooth and deterministic. The idealized work curve looks something like this in our heads:
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