Flashback to Basics Friday! Bandwidth...
April 25, 2016
I’ve been thinking for a while (yes, that explains the burning smell) that we should be covering some of the basics of PCI Express here at ExpressYourself in addition to “just” the new stuff. After reading today’s posting, please let me know in the comments whether this is a good idea or not…
One of the questions I’ve been getting a lot recently is along the lines of “How many lanes and of what ‘generation’ of PCI Express do I need?”
This is a fairly straightforward question, and while coming up with a good first-order estimation is also fairly straightforward, it’s not necessarily obvious in the PCI Express specification. Let’s start with the “raw” data rate, which is fairly easy:
To read the full article, click here
Related Semiconductor IP
- PCIe - PCI Express Controller
- Scalable Switch Intel® FPGA IP for PCI Express
- Multichannel DMA Intel FPGA IP for PCI Express*
- PCI Express Gen5 SERDES PHY on Samsung 8LPP
- PCI Express Gen4 SERDES PHY on Samsung 7LPP
Related Blogs
- Flashback to Basics Friday! Bifurcation...
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Black Friday and the Predicted Semiconductor Shortages
- MoSys Fires Up the Bandwidth Engine
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP